Yield evaluation of analog placement with arbitrary capacitor ratio

Jwu E. Chen, Pei Wen Luo, Chin Long Wey

研究成果: 書貢獻/報告類型會議論文篇章同行評審

10 引文 斯高帕斯(Scopus)

摘要

Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.

原文???core.languages.en_GB???
主出版物標題Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
頁面179-184
頁數6
DOIs
出版狀態已出版 - 2009
事件10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA, United States
持續時間: 16 3月 200918 3月 2009

出版系列

名字Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???10th International Symposium on Quality Electronic Design, ISQED 2009
國家/地區United States
城市San Jose, CA
期間16/03/0918/03/09

指紋

深入研究「Yield evaluation of analog placement with arbitrary capacitor ratio」主題。共同形成了獨特的指紋。

引用此