@inproceedings{ecfbadf77be24fe2946ddae6de7fa16a,
title = "Yield-award placement optimization for Switched-Capacitor analog integrated circuits",
abstract = "Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.",
keywords = "layout generator, physical realization, random variation, spatial correlation, Yield-Award",
author = "Huang, {Chien Chih} and Chen, {Jwu E.} and Luo, {Pei Wen} and Wey, {Chin Long}",
year = "2011",
doi = "10.1109/SOCC.2011.6085127",
language = "???core.languages.en_GB???",
isbn = "9781457716164",
series = "International System on Chip Conference",
pages = "170--173",
booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2011",
note = "24th IEEE International System on Chip Conference, SOCC 2011 ; Conference date: 26-09-2011 Through 28-09-2011",
}