Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits

Yu Guang Chen, Kuan Yu Lai, Ming Chao Lee, Yiyu Shi, Wing Kai Hon, Shih Chieh Chang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

Through Silicon Via (TSV) is a critical enabling technique in three-dimensional integrated circuits (3D ICs). However, it may suffer from many reliability issues. Various fault-tolerance mechanisms have been proposed in literature to improve yield, at the cost of significant area overhead. In this paper, we focus on the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs under yield and timing constraints to minimize the total area overhead. We show that such problem can be modeled through constrained graph decomposition. An efficient heuristic is further developed to address this problem. Experimental results show that under the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to 38%, compared with a seemingly more intuitive nearest-neighbor based heuristic.

原文???core.languages.en_GB???
主出版物標題Proceedings - Design, Automation and Test in Europe, DATE 2014
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9783981537024
DOIs
出版狀態已出版 - 2014
事件17th Design, Automation and Test in Europe, DATE 2014 - Dresden, Germany
持續時間: 24 3月 201428 3月 2014

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
ISSN(列印)1530-1591

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???event.eventtypes.event.conference???17th Design, Automation and Test in Europe, DATE 2014
國家/地區Germany
城市Dresden
期間24/03/1428/03/14

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