摘要
A wide-range synchronous mirror delay (SMD) with arbitrary input duty cycle is presented. The proposed SMD utilises the time-to-digital converter for a frequency-range selector and a multiband delay monitor circuit to achieve a wide range of operating frequencies. The simulation results show that the operating frequency is from 200 MHz to 1 GHz and the static phase error is 6.7 ps. The locking time is less than eight clock cycles: two cycles with coarse tune and six cycles with fine tune.
原文 | ???core.languages.en_GB??? |
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頁(從 - 到) | 665-667 |
頁數 | 3 |
期刊 | Electronics Letters |
卷 | 44 |
發行號 | 11 |
DOIs | |
出版狀態 | 已出版 - 2008 |