Wafer map defect classification with depthwise separable convolutions

Tsung Han Tsai, Yu Chen Lee

研究成果: 書貢獻/報告類型會議論文篇章同行評審

9 引文 斯高帕斯(Scopus)

摘要

In the IC design process, the test process is the main factor of production cost. Existing tests rely on additional analysis of testing result data by the engineer to determine the status of the process. Thus it could take an additional amount of time and cannot make adjustments of the process immediately. Wafer map defect recognition is an import part of semiconductor. There is lots of information in wafer maps which can quickly help engineers to identify what failure type it is. The location of the error point is graphical represented and the relationship of these points contains the feature of this map. In this paper, we proposed a classifier with reduced-weight architecture based on depthwise separable convolutions. The entire work is verified by using the real-world wafer map dataset (WM-811K). The accuracy is 96.63% in test set.

原文???core.languages.en_GB???
主出版物標題2020 IEEE International Conference on Consumer Electronics, ICCE 2020
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728151861
DOIs
出版狀態已出版 - 1月 2020
事件2020 IEEE International Conference on Consumer Electronics, ICCE 2020 - Las Vegas, United States
持續時間: 4 1月 20206 1月 2020

出版系列

名字Digest of Technical Papers - IEEE International Conference on Consumer Electronics
2020-January
ISSN(列印)0747-668X

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???event.eventtypes.event.conference???2020 IEEE International Conference on Consumer Electronics, ICCE 2020
國家/地區United States
城市Las Vegas
期間4/01/206/01/20

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