VLSI implementation of visual block pattern truncation coding

Yuan Chen Liu; Tsung Han Tsai; Po Cheng Wu; Liang Gee Chen

VLSI implementation of visual block pattern truncation coding

Yuan Chen Liu, Tsung Han Tsai, Po Cheng Wu, Liang Gee Chen

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

摘要

The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

原文	???core.languages.en_GB???
頁（從 - 到）	36-37
頁數	2
期刊	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
出版狀態	已出版 - 1998
事件	Proceedings of the 1998 17th Conference on Consumer Electronics - Los Angeles, CA, USA 持續時間: 2 6月 1998 → 4 6月 1998

引用此

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title = "VLSI implementation of visual block pattern truncation coding",

abstract = "The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.",

author = "Liu, {Yuan Chen} and Tsai, {Tsung Han} and Wu, {Po Cheng} and Chen, {Liang Gee}",

year = "1998",

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pages = "36--37",

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AU - Liu, Yuan Chen

AU - Tsai, Tsung Han

AU - Wu, Po Cheng

AU - Chen, Liang Gee

PY - 1998

Y1 - 1998

N2 - The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

AB - The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

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M3 - 會議論文

AN - SCOPUS:0031625591

SN - 0747-668X

SP - 36

EP - 37

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

T2 - Proceedings of the 1998 17th Conference on Consumer Electronics

Y2 - 2 June 1998 through 4 June 1998

ER -

VLSI implementation of visual block pattern truncation coding

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