VLSI implementation of 3-D sound generator

An Nan Suen; Jhing Fa Wang; Jia Ching Wang

doi:10.1109/30.628694

VLSI implementation of 3-D sound generator

An Nan Suen
, Jhing Fa Wang
, Jia Ching Wang

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

3 引文斯高帕斯（Scopus）

摘要

In this paper we propose the VLSI architecture for the 3-D sound generator. The main feature of the proposed 3-D sound architecture is the high performance for sound source localization. We maintain high localization cues owing to the long length of head related transfer function (HRTF). Though short length HRTF can reduce computation load, the localization cues will degrade. Fast algorithm and efficient architecture are proposed to generate 3-D sound by long length HRTF at 44.1k sampling rate. In addition, crossfading effect is used for sound source smoothly moving.

原文	???core.languages.en_GB???
頁（從 - 到）	679-688
頁數	10
期刊	IEEE Transactions on Consumer Electronics
卷	43
發行號	3
DOIs	https://doi.org/10.1109/30.628694
出版狀態	已出版 - 1997

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10.1109/30.628694

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VLSI implementation of 3-D sound generator

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