VLSI implementation of 3-D sound generator

An Nan Suen, Jhing Fa Wang, Jia Ching Wang

研究成果: 雜誌貢獻會議論文同行評審


A high performance VLSI architecture is proposed for the 3D sound generation chip. A single 3D sound chip design reduces the cost and size of many audio systems. The proposed 3D sound VLSI architecture has the following merits: excellent accuracy results due to the accuracy studies for the finite word length; high speed operations owing to the high performance concurrent processing structure; and real-time response for 44.1 KHz sampling data.

頁(從 - 到)296-297
期刊Digest of Technical Papers - IEEE International Conference on Consumer Electronics
出版狀態已出版 - 1997
事件Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA
持續時間: 11 6月 199713 6月 1997


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