@inproceedings{6b73802e391f46908ca6d064166f7f21,
title = "VLSI design of sequential minimal optimization algorithm for SVM learning",
abstract = "The sequential minimal optimization (SMO) algorithm has been widely used for training the support vector machine (SVM). In this paper, we present the first chip design for sequential minimal optimization. This chip is implemented as an intellectual property (IP) core, suitable to be utilized in an SVM-based recognition system on a chip. The proposed SMO chip has been tested to be fully functional, using a prototype system based on the Altera DE2 board with Cyclone II 2C70 FPGA (field-programmable gate array) .",
author = "Kuan, {Ta Wen} and Wang, {Jhing Fa} and Wang, {Jia Ching} and Gu, {Gaung Hui}",
year = "2009",
doi = "10.1109/ISCAS.2009.5118311",
language = "???core.languages.en_GB???",
isbn = "9781424438280",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "2509--2512",
booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",
note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",
}