VLSI design of an SVM learning core on sequential minimal optimization algorithm

Ta Wen Kuan; Jhing Fa Wang; Jia Ching Wang; Po Chuan Lin; Gaung Hui Gu

doi:10.1109/TVLSI.2011.2107533

VLSI design of an SVM learning core on sequential minimal optimization algorithm

Ta Wen Kuan
, Jhing Fa Wang
, Jia Ching Wang
, Po Chuan Lin
, Gaung Hui Gu

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

58 引文斯高帕斯（Scopus）

摘要

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

原文	???core.languages.en_GB???
文章編號	5713858
頁（從 - 到）	673-683
頁數	11
期刊	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
卷	20
發行號	4
DOIs	https://doi.org/10.1109/TVLSI.2011.2107533
出版狀態	已出版 - 4月 2012

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10.1109/TVLSI.2011.2107533

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title = "VLSI design of an SVM learning core on sequential minimal optimization algorithm",

abstract = "The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.",

keywords = "Field-programmable gate array (FPGA), VLSI design, sequential minimal optimization (SMO), support vector machine (SVM)",

author = "Kuan, \{Ta Wen\} and Wang, \{Jhing Fa\} and Wang, \{Jia Ching\} and Lin, \{Po Chuan\} and Gu, \{Gaung Hui\}",

note = "Funding Information: Manuscript received August 08, 2010; revised November 16, 2010; accepted December 30, 2010. Date of publication February 17, 2011; date of current version March 12, 2012. This work was supported by the National Science Council under Grant NSC99-2218-E-006-001.",

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AU - Kuan, Ta Wen

AU - Wang, Jhing Fa

AU - Wang, Jia Ching

AU - Lin, Po Chuan

AU - Gu, Gaung Hui

N1 - Funding Information: Manuscript received August 08, 2010; revised November 16, 2010; accepted December 30, 2010. Date of publication February 17, 2011; date of current version March 12, 2012. This work was supported by the National Science Council under Grant NSC99-2218-E-006-001.

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N2 - The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

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KW - Field-programmable gate array (FPGA)

KW - VLSI design

KW - sequential minimal optimization (SMO)

KW - support vector machine (SVM)

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VLSI design of an SVM learning core on sequential minimal optimization algorithm

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