VLSI design of an SVM learning core on sequential minimal optimization algorithm

Ta Wen Kuan, Jhing Fa Wang, Jia Ching Wang, Po Chuan Lin, Gaung Hui Gu

研究成果: 雜誌貢獻期刊論文同行評審

55 引文 斯高帕斯(Scopus)

摘要

The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array.

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文章編號5713858
頁(從 - 到)673-683
頁數11
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
20
發行號4
DOIs
出版狀態已出版 - 4月 2012

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