VLSI Design for SVM-Based Speaker Verification System

Jia Ching Wang, Li Xun Lian, Yan Yu Lin, Jia Hao Zhao

研究成果: 雜誌貢獻期刊論文同行評審

24 引文 斯高帕斯(Scopus)

摘要

This brief presents the chip implementation of a support vector machine (SVM)-based speaker verification system. The proposed chip comprises a speaker feature extraction (SFE) module, an SVM module, and a decision module. The SFE module performs autocorrelation analysis, linear predictive coefficient (LPC) extraction, and LPC-to-cepstrum conversion. The SVM module includes a Gaussian kernel unit and a scaling unit. The purpose of the Gaussian kernel unit is first to evaluate the kernel value of a test vector and a support vector. Four Gaussian kernel processing elements (GK-PEs) are designed to process four support vectors simultaneously. Each GK-PE is designed in the pipeline fashion and is capable of performing 2-norm and exponential operations. An enhanced CORDIC architecture is proposed to calculate the exponential value. As well as the Gaussian kernel unit, a scaling unit is also developed for use in the SVM module. The scaling unit is used to perform scaling multiplications and the remaining operations of SVM decision value evaluation. Finally, the decision module accumulates the frame scores that are generated by all of the test frames, and then compare it with a threshold to see if the test utterance is spoken by the claimed speaker. This designed chip is characterized by its high speed and its ability to handle a large number of support vectors in the SVM. The prototype chip is a semicustom chip that is fabricated using Taiwan Semiconductor Manufacturing Company 0.90-nm CMOS technology on a die with a size of ~7.9 × 7.9 mm2.

原文???core.languages.en_GB???
文章編號6860311
頁(從 - 到)1355-1359
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
23
發行號7
DOIs
出版狀態已出版 - 1 7月 2015

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