TY - JOUR

T1 - VLSI design for MPEG-4 shape coding using a contour-based binary motion estimation algorithm

AU - Tsai, T. H.

AU - Chen, C. P.

PY - 2008

Y1 - 2008

N2 - An efficient architecture with the fast algorithm for MPEG-4 shape coding is proposed. The authors apply the fast shape coding algorithm, with contour-based binary motion estimation (CBBME), which is based on the properties of a boundary mask. By using the block-matching motion estimation and the extended approach on centre-biased motion vector distribution with shrinking of the search range, a large number of search points in BME can be skipped. Based on this algorithm, a dedicated architecture design using the proposed CBBME algorithm is developed. With certain optimisation and design considerations, the memory access and processing cycles can be reduced. The average number of clock cycles for the processing of one binary alpha block is only 1708, which is only 56% of the previous design. In addition, a prototyping chip for shape coding is implemented and verified. The die area is 2.4 × 2.4 mm2 with TSMC 0.18 μm CMOS technology and the maximum clock frequency is 53 MHz.

AB - An efficient architecture with the fast algorithm for MPEG-4 shape coding is proposed. The authors apply the fast shape coding algorithm, with contour-based binary motion estimation (CBBME), which is based on the properties of a boundary mask. By using the block-matching motion estimation and the extended approach on centre-biased motion vector distribution with shrinking of the search range, a large number of search points in BME can be skipped. Based on this algorithm, a dedicated architecture design using the proposed CBBME algorithm is developed. With certain optimisation and design considerations, the memory access and processing cycles can be reduced. The average number of clock cycles for the processing of one binary alpha block is only 1708, which is only 56% of the previous design. In addition, a prototyping chip for shape coding is implemented and verified. The die area is 2.4 × 2.4 mm2 with TSMC 0.18 μm CMOS technology and the maximum clock frequency is 53 MHz.

UR - http://www.scopus.com/inward/record.url?scp=56149107868&partnerID=8YFLogxK

U2 - 10.1049/iet-cds:20080048

DO - 10.1049/iet-cds:20080048

M3 - 期刊論文

AN - SCOPUS:56149107868

VL - 2

SP - 429

EP - 438

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 5

ER -