VLSI architecture design for concatenative speech synthesizer

Li Ping Chu, Jia Ching Wang, Jhing Fa Wang

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a VLSI architecture for Mandarin speech synthesis. For the natural synthesized speech, subsyllable based synthesis units are recorded in advance. The synthesized speech is obtained by suitably concatenating the synthesis units. The TD-PSOLA (Time Domain Pitch Synchronous Overlap-and-Add) approach is used to perform the prosody modification. The proposed VLSI architecture includes two parts: the TD-PSOLA module and the synthesized pitch period generator. In the TD-PSOLA module, we also present a fast CORDIC architecture which is five times faster than the conventional method.

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主出版物標題TENCON 2005 - 2005 IEEE Region 10 Conference
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)0780393112, 9780780393110
DOIs
出版狀態已出版 - 2005
事件TENCON 2005 - 2005 IEEE Region 10 Conference - Melbourne, Australia
持續時間: 21 11月 200524 11月 2005

出版系列

名字IEEE Region 10 Annual International Conference, Proceedings/TENCON
2007
ISSN(列印)2159-3442
ISSN(電子)2159-3450

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???event.eventtypes.event.conference???TENCON 2005 - 2005 IEEE Region 10 Conference
國家/地區Australia
城市Melbourne
期間21/11/0524/11/05

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