VLSI architecture design for BNN speech recognition

Jia Ching Wang, Jhing Fa Wang, Fan Min Li

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

In this paper, we present the efficient VLSI architecture for the stand-alone application of the speech recognition system based on Bayesian neural network (BNN). Consider the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed based on one or multiple fundamental distance units. Template-serial and template-parallel architectures are both proposed to be associated with the BDU to perform the recognition procedure. In accordance with the number of the basic recognition units and the adopted BDU architecture, the choice is made between template-serial and template-parallel architectures so that the frame synchronous feature can be achieved in an efficient way.

原文???core.languages.en_GB???
主出版物標題Proceedings of the IASTED International Conference on Signal Processing, Pattern Recognition, and Applications
編輯M.H. Hamza
頁面200-204
頁數5
出版狀態已出版 - 2003
事件Proceedings of the IASTED International Conference on Signal Processing, Pattern Recognition and Applications - Rhodes, Greece
持續時間: 30 6月 20032 7月 2003

出版系列

名字Proceedings of the IASTED International Conference on Signal Processing, Pattern Reconition, and Applications

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???event.eventtypes.event.conference???Proceedings of the IASTED International Conference on Signal Processing, Pattern Recognition and Applications
國家/地區Greece
城市Rhodes
期間30/06/032/07/03

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