Vernier caliper and equivalent-signal sampling for built-in jitter measurement system

Shu Yu Jiang, Chan Wei Huang, Yu Lung Lo, Kuo Hsing Cheng

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 μm CMOS process. Furthermore these techniques are successfully verified in 14 ps circuit resolution and a 500*750 μm chip area for the 100-400 MHz measurement range.

原文???core.languages.en_GB???
頁(從 - 到)389-400
頁數12
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E92-A
發行號2
DOIs
出版狀態已出版 - 2月 2009

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