Verification pattern generation for core-based design using port order fault model

Shing Wu Tung, Jing Yang Jou

研究成果: 雜誌貢獻會議論文同行評審

11 引文 斯高帕斯(Scopus)


The lack of information about core's internal structure is The designers must rely solely on the test set distributed by the core provider. Sometimes the stuck at fault (SAF) model and automatic test pattern generation (ATPG) are used to generate test vectors for those pre-defined blocks. However, a SAF test set could waste lots of time to verify the pre-verified internal structure of the cores. Therefore, in order to reduce the core-based design verification time, we should adopt the connectivity-based port order fault (POF) model instead of the stuck at fault model. In this paper, we compare the POF model with the SAF model and propose a method that the POF test set for functional verification can be generated by using the SAF-based ATPG tools with proper assignment of don't care terms in inputs.

頁(從 - 到)402-407
期刊Proceedings of the Asian Test Symposium
出版狀態已出版 - 1998
事件Proceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore
持續時間: 2 12月 19984 12月 1998


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