@inproceedings{2c6b572a7f1547fdad7b34e7963e971e,
title = "Verification of systolic architecture designs",
abstract = "We present a Prolog-based verifier, VSTA, for formal specification and verification of systolic architectures. This specific CAD tool is developed to produce sound and efficient verification process and provide short-cuts to justify systolic array designs. We describe how a systolic array for 2-D matrix multiplication and LU decomposition can be specified and verified with respect to its algorithm.",
author = "Fuyau Lin and Timothy Shih",
note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 1992.; 4th International Parallel Architectures and Languages Europe Conference, PARLE 1992 ; Conference date: 15-06-1992 Through 18-06-1992",
year = "1992",
doi = "10.1007/3-540-55599-4_100",
language = "???core.languages.en_GB???",
isbn = "9783540555995",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "381--396",
editor = "Daniel Etiemble and Jean-Claude Syre",
booktitle = "PARLE 1992 Parallel Architectures and Languages Europe - 4th International PARLE Conference, Proceedings",
}