Two-Level logic minimization for low power

Jyh Mou Tseng Itri, Jing Yang Jou

研究成果: 雜誌貢獻期刊論文同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper we present a complete Boolean method for reducing the power consumption in two-level combinational circuits. The two-level logic optimizer performs the logic minimization for low power targeting static PLA, general logic gates, and dynamic PLA implementations. We modify the espresso algorithm by adding our heuristics, which bias logic minimization toward lowering power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. The experimental results are promising.

原文???core.languages.en_GB???
頁(從 - 到)52-69
頁數18
期刊ACM Transactions on Design Automation of Electronic Systems
4
發行號1
DOIs
出版狀態已出版 - 1999

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