TRANS: A fast and memory-efficient path delay fault simulator

Meng Chiy Lin, Jwu E. Chen, Chung Len Lee

研究成果: 書貢獻/報告類型會議論文篇章同行評審

3 引文 斯高帕斯(Scopus)

摘要

For path fault testing, simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits except c6288 for one million patterns, TRANS runs within 2.5 hours and 2.2 mega-bytes for each circuit. Comparing the experimental results with one of DAC'89, TRANS gets 85 times the gain of memory-speed product.

原文???core.languages.en_GB???
主出版物標題Proceedings of the European Design and Test Conference
編輯 Anon
發行者Publ by IEEE
頁面508-512
頁數5
ISBN(列印)0818654112
出版狀態已出版 - 1994
事件Proceedings of the European Design and Test Conference - Paris, Fr
持續時間: 28 2月 19943 3月 1994

出版系列

名字Proceedings of the European Design and Test Conference

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???event.eventtypes.event.conference???Proceedings of the European Design and Test Conference
城市Paris, Fr
期間28/02/943/03/94

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