To verify manufacturing yield by testing

Mill Jer Wang, Jwu E. Chen, Yung Yuan Chen

研究成果: 雜誌貢獻會議論文同行評審

2 引文 斯高帕斯(Scopus)


The effect of test errors should be canceled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the yield data obtained from engineering stage, the upper and lower bounds of chip yield are calculated after determining the variance of defect density and used to diagnose the results after wafer sort while in production. One ASIC product is used to validate this yield analysis procedure. This work can assist the ASIC design center to determine a manufacturing laboratory beginning the design and to control the chip area in the period of circuit design.

頁(從 - 到)385-390
期刊Proceedings of the Asian Test Symposium
出版狀態已出版 - 1994
事件Proceedings of the 3rd Asian Test Symposium - Nara, Jpn
持續時間: 15 11月 199417 11月 1994


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