Timing-driven partial scan

Jing Yang Jou, Kwang Ting Cheng

研究成果: 書貢獻/報告類型會議論文篇章同行評審

14 引文 斯高帕斯(Scopus)

摘要

A partial scan approach that aims to reduce both area overhead and performance degradation caused by test logic is presented. Given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization is minimized. For circuits synthesized by automatic synthesis tools, the authors suggest a novel design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. For meeting both performance and testability requirements, this design flow produces designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization. Experimental results on the ISCAS'89 sequential circuits are presented as well as comparisons between the proposed method and previous methods.

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主出版物標題1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
發行者Publ by IEEE
頁面404-407
頁數4
ISBN(列印)0818621575
出版狀態已出版 - 1992
事件1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
持續時間: 11 11月 199114 11月 1991

出版系列

名字1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

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???event.eventtypes.event.conference???1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
城市Santa Clara, CA, USA
期間11/11/9114/11/91

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