The understanding of strain-induced device degradation in advanced MOSFETs with process-induced strain technology of 65nm node and beyond

In this paper, the origin of the strained-induced degradation in the MOSFETs with process-induced strain has been investigated by the I _D-RTN (Drain Current Random Telegraph Noise)technique. The process-induced strain on devices will make worse the device reliability, as reported in [1-2]. First, the I_D-RTN has been employed to study the reliability of two different types of strain devices, i.e., the CESL strain and SiC S/D strain on nMOSFETs. Both CESL and SiC S/D nMOSFETs exhibit poorer reliability compared to bulk devices. However, their impacts to the much worse degradation are different. Results demonstrated that, for the strain in CESL device, it introduced extra mobility scattering in the vertical direction, while in SiC S/D device, the tensile strain along the channel causes an increase of trap generation via the horizontal field only. The CESL process introduces an additional compressive strain vertical to the channel such that it shows much worse reliability than the SiC S/D ones.