The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found

The impact of multi-level RTN on SRAM cells bas been experimentally demonstrated on both planar and trigate CMOS devices. First, to study multi-level RTN, a simple experimental method has been developed to take the 2D profiling of multi-traps in both oxide depth (vertical) and channel(lateral) directions in the gate oxide. Then, the role of traps in the switching mechanisms of SRAM cells has also been examined. Results show that the multi-traps will degrade RSNM (read static noise margin), as well as cause transition failure in SRAM operations. This is the first being observed and reported that will be considered as a major criterion in the future low voltage design of SRAM cells.