The understanding of gate capacitance matching on achieving a high performance NC MOSFET with sufficient mobility

C. K. Chiang, P. Husan, Y. C. Lou, F. L. Li, E. R. Hsieh, C. H. Liu, Steve S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

We develop experimental approaches to quantitatively extract the negative capacitance of MIM in a gate stacked NCFET. It was found that the NC effect is highly dependent on the grain and dipole behaviors with different annealing temperature. Also, to achieve a better design of high-performance NCFET, we explore not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it adversely generated the degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable performance can be achieved.

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主出版物標題2019 Silicon Nanoelectronics Workshop, SNW 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9784863487024
DOIs
出版狀態已出版 - 6月 2019
事件24th Silicon Nanoelectronics Workshop, SNW 2019 - Kyoto, Japan
持續時間: 9 6月 201910 6月 2019

出版系列

名字2019 Silicon Nanoelectronics Workshop, SNW 2019

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???event.eventtypes.event.conference???24th Silicon Nanoelectronics Workshop, SNW 2019
國家/地區Japan
城市Kyoto
期間9/06/1910/06/19

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