The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Wei Bin Yang, Shu Chang Kuo, Yuan Hua Chu, Kuo Hsing Cheng

研究成果: 書貢獻/報告類型會議論文篇章同行評審

5 引文 斯高帕斯(Scopus)

摘要

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

原文???core.languages.en_GB???
主出版物標題Proceedings of the 2005 European Conference on Circuit Theory and Design
頁面193-196
頁數4
DOIs
出版狀態已出版 - 2005
事件2005 European Conference on Circuit Theory and Design - Cork, Ireland
持續時間: 28 8月 20052 9月 2005

出版系列

名字Proceedings of the 2005 European Conference on Circuit Theory and Design
3

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???event.eventtypes.event.conference???2005 European Conference on Circuit Theory and Design
國家/地區Ireland
城市Cork
期間28/08/052/09/05

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