TY - GEN
T1 - The issues on the power consumption of Trigate FinFET
T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
AU - Chung, Steve S.
AU - Hsieh, E. R.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/5
Y1 - 2017/10/5
N2 - A theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
AB - A theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
UR - http://www.scopus.com/inward/record.url?scp=85045067482&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2017.8060064
DO - 10.1109/IPFA.2017.8060064
M3 - 會議論文篇章
AN - SCOPUS:85045067482
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 1
EP - 4
BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 July 2017 through 7 July 2017
ER -