The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond

E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung

研究成果: 書貢獻/報告類型會議論文篇章同行評審

2 引文 斯高帕斯(Scopus)

摘要

A 4kb macro of One Time Programming (OTP) memory, implemented by a new breakdown, named dielectric fuse (dFuse) breakdown, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 1.5T per cell with 7.5F-2. The experimental results show that dFuse macro exhibits high programming (PGM) speed of 100ns at 4V, read time smaller than 10ns at 0.75V, and excellent data retention under one-month baking at 150°C. More importantly, the program voltage is weakly dependent on the environmental temperature, suitable for automotive applications. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the storage purpose in IoT and 5G era.

原文???core.languages.en_GB???
主出版物標題2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面C208-C209
ISBN(電子)9784863487185
DOIs
出版狀態已出版 - 6月 2019
事件33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
持續時間: 9 6月 201914 6月 2019

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2019-June

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???event.eventtypes.event.conference???33rd Symposium on VLSI Circuits, VLSI Circuits 2019
國家/地區Japan
城市Kyoto
期間9/06/1914/06/19

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