摘要
A measurement methodology involving the synchronous switching of gate to source voltage and drain to source voltage (VDS) was proposed for determining the shift of threshold voltage after an AlGaN/GaN heterostructure transistor endures high VDS off-state stress. The measurement results indicated slow electron detrapping behavior. The trap level was determined as (EC - 0.6 eV). Simulation tool was used to analyze the measurement results. The simulation results were consistent with the experimental results; and a relationship between the buffer trap and threshold voltage shift over time was observed.
原文 | ???core.languages.en_GB??? |
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文章編號 | 033503 |
期刊 | Applied Physics Letters |
卷 | 104 |
發行號 | 3 |
DOIs | |
出版狀態 | 已出版 - 20 1月 2014 |