Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

研究成果: 書貢獻/報告類型會議論文篇章同行評審

21 引文 斯高帕斯(Scopus)

摘要

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

原文???core.languages.en_GB???
主出版物標題2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728122601
DOIs
出版狀態已出版 - 10月 2019
事件32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands
持續時間: 2 10月 20194 10月 2019

出版系列

名字2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

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???event.eventtypes.event.conference???32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
國家/地區Netherlands
城市Noordwijk
期間2/10/194/10/19

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