Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai; Jin Fu Li; Chun Lung Hsu; Chi Tien Sun

doi:10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs

Tsai Ling Tsai, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

23 引文斯高帕斯（Scopus）

摘要

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

原文	???core.languages.en_GB???
主出版物標題	2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781728122601
DOIs	https://doi.org/10.1109/DFT.2019.8875487
出版狀態	已出版 - 10月 2019
事件	32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 - Noordwijk, Netherlands 持續時間: 2 10月 2019 → 4 10月 2019

出版系列

名字	2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019
國家/地區	Netherlands
城市	Noordwijk
期間	2/10/19 → 4/10/19

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10.1109/DFT.2019.8875487

堆疊式記憶體測試與可靠度增強技術(3/3)
Li, J.-F. (PI)
1/08/18 → 31/07/19
研究計畫: Research
應用於物聯網之新興非揮發性記憶體測試技術(3/3)
Li, J.-F. (PI)
1/08/18 → 31/07/19
研究計畫: Research

引用此

Tsai, T. L., Li, J. F., Hsu, C. L., & Sun, C. T. (2019). Testing of in-memory-computing 8T SRAMs. 於 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019 文章 8875487 (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2019.8875487

Tsai, Tsai Ling ; Li, Jin Fu ; Hsu, Chun Lung 等. / Testing of in-memory-computing 8T SRAMs. 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

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title = "Testing of in-memory-computing 8T SRAMs",

abstract = "To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.",

author = "Tsai, {Tsai Ling} and Li, {Jin Fu} and Hsu, {Chun Lung} and Sun, {Chi Tien}",

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Tsai, TL, Li, JF , Hsu, CL & Sun, CT 2019, Testing of in-memory-computing 8T SRAMs. 於 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019., 8875487, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019, Institute of Electrical and Electronics Engineers Inc., 32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019, Noordwijk, Netherlands, 2/10/19. https://doi.org/10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs. / Tsai, Tsai Ling; Li, Jin Fu ; Hsu, Chun Lung 等.
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8875487 (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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PY - 2019/10

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AB - To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. Various IMC static random access memories (SRAMs) were reported. In this paper, we propose test method for IMC 8T SRAMs with NAND, NOR, and XOR logic operations. The IMC 8T SRAMs should be tested in memory mode and computing mode. A March C-8 test algorithm is proposed to cover typical functional faults and process variation-induced faults of the IMC 8T SRAMs.

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Tsai TL, Li JF , Hsu CL, Sun CT. Testing of in-memory-computing 8T SRAMs. 於 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8875487. (2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019). doi: 10.1109/DFT.2019.8875487

Testing of in-memory-computing 8T SRAMs

摘要

出版系列

???event.eventtypes.event.conference???

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指紋

專案

堆疊式記憶體測試與可靠度增強技術(3/3)

應用於物聯網之新興非揮發性記憶體測試技術(3/3)

引用此