Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

Jin Fu Li

doi:10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

Jin Fu Li

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

摘要

Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.

原文	???core.languages.en_GB???
主出版物標題	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
編輯	Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9798350315004
DOIs	https://doi.org/10.1109/DFT59622.2023.10313537
出版狀態	已出版 - 2023
事件	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Juan-Les-Pins, France 持續時間: 3 10月 2023 → 5 10月 2023

出版系列

名字	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN（列印）	2576-1501
ISSN（電子）	2765-933X

???event.eventtypes.event.conference???

???event.eventtypes.event.conference???	36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
國家/地區	France
城市	Juan-Les-Pins
期間	3/10/23 → 5/10/23

存取文件

10.1109/DFT59622.2023.10313537

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)
Li, J.-F. (PI)
1/08/25 → 31/07/26
研究計畫: Research

引用此

Li, J. F. (2023). Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. 於 L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (編輯), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT59622.2023.10313537

Li, Jin Fu. / Testing of Computing-In Memories : Faults, Test Algorithms, and Design-for-Testability. 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. 編輯 / Luca Cassano ; Mihalis Psarakis ; Marcello Traiola ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

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title = "Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability",

abstract = "Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.",

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Li, JF 2023, Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. 於 L Cassano, M Psarakis, M Traiola & A Bosio (編輯), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, Institute of Electrical and Electronics Engineers Inc., 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, 3/10/23. https://doi.org/10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. / Li, Jin Fu.
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. 編輯 / Luca Cassano; Mihalis Psarakis; Marcello Traiola; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

研究成果: 書貢獻/報告類型 › 會議論文篇章 › 同行評審

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AB - Computing-in memories (CIMs) support memory and computing functions. The operations of computing function are much different from the read/write operations of conventional memories, e.g., multiple wordlines are activated, specific sensing methods, and so on. Those cause that the CIM has computing faults. Conventional march tests for memories cannot cover the computing faults and new test algorithms are needed. In this embedded tutorial, therefore, we introduce fault modeling and test development methods for CIMs with logic operations. Furthermore, we will provide perspectives on the design-for-testability techniques for CIMs as well.

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Li JF. Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. 於 Cassano L, Psarakis M, Traiola M, Bosio A, 編輯, 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT59622.2023.10313537

Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability

摘要

出版系列

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指紋

專案

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)

引用此