Testable PLA design with low overhead and ease of test generation

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the 'don't care' assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved.

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主出版物標題1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
發行者Publ by IEEE
頁面450-453
頁數4
ISBN(列印)0818608722
出版狀態已出版 - 1988

出版系列

名字1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

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