Testable and fault tolerant design for FFT networks

Jin Fu Li; Cheng Wen Wu

Testable and fault tolerant design for FFT networks

Jin Fu Li, Cheng Wen Wu

電機工程學系

研究成果: 雜誌貢獻 › 會議論文 › 同行評審

3 引文斯高帕斯（Scopus）

摘要

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

原文	???core.languages.en_GB???
頁（從 - 到）	201-209
頁數	9
期刊	IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
出版狀態	已出版 - 1999
事件	Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA 持續時間: 1 11月 1999 → 3 11月 1999

引用此

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AU - Wu, Cheng Wen

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N2 - We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

AB - We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead - only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low - about 4% for 16-bit numbers regardless of the FFT network size.

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M3 - 會議論文

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JO - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

JF - IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

T2 - Proceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99)

Y2 - 1 November 1999 through 3 November 1999

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Testable and fault tolerant design for FFT networks

摘要

指紋

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