Testable and fault tolerant design for FFT networks

Jin Fu Li, Cheng Wen Wu

研究成果: 書貢獻/報告類型會議論文篇章同行評審

摘要

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size.

原文???core.languages.en_GB???
主出版物標題Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
發行者Institute of Electrical and Electronics Engineers Inc.
頁面201-209
頁數9
ISBN(電子)076950325X, 9780769503257
DOIs
出版狀態已出版 - 1999
事件1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States
持續時間: 1 11月 19993 11月 1999

出版系列

名字Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

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???event.eventtypes.event.conference???1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
國家/地區United States
城市Albuquerque
期間1/11/993/11/99

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