Testability exploration of 3-D RAMs and CAMs

Yu Jen Huang, Jin Fu Li

研究成果: 書貢獻/報告類型會議論文篇章同行評審

8 引文 斯高帕斯(Scopus)

摘要

Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.

原文???core.languages.en_GB???
主出版物標題Proceedings of the 18th Asian Test Symposium, ATS 2009
頁面397-402
頁數6
DOIs
出版狀態已出版 - 2009
事件18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan
持續時間: 23 11月 200926 11月 2009

出版系列

名字Proceedings of the Asian Test Symposium
ISSN(列印)1081-7735

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???event.eventtypes.event.conference???18th Asian Test Symposium, ATS 2009
國家/地區Taiwan
城市Taichung
期間23/11/0926/11/09

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