@inproceedings{d5cb7999f9ac4908a127375da35a83a7,
title = "Test cost optimization technique for the pre-bond test of 3D ICs",
abstract = "Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.",
author = "Chen, {Yong Xiao} and Huang, {Yu Jen} and Li, {Jin Fu}",
year = "2012",
doi = "10.1109/VTS.2012.6231087",
language = "???core.languages.en_GB???",
isbn = "9781467310741",
series = "Proceedings of the IEEE VLSI Test Symposium",
pages = "102--107",
booktitle = "Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012",
note = "null ; Conference date: 23-04-2012 Through 26-04-2012",
}