Test and repair scheduling for built-in self-repair RAMs in SOCs

Chih Sheng Hou, Jin Fu Li, Che Wei Chou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

6 引文 斯高帕斯(Scopus)

摘要

Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC'02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm.

原文???core.languages.en_GB???
主出版物標題Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
頁面3-7
頁數5
DOIs
出版狀態已出版 - 2010
事件5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010 - Ho Chi Minh City, Viet Nam
持續時間: 13 1月 201015 1月 2010

出版系列

名字Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010

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???event.eventtypes.event.conference???5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
國家/地區Viet Nam
城市Ho Chi Minh City
期間13/01/1015/01/10

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