TY - JOUR
T1 - System level integration methodology for MPEG-2 audio decoder with embedded RISC core
AU - Tsai, Tsung Han
AU - Chen, Liang Gee
AU - Wu, Ren Jr
PY - 1999
Y1 - 1999
N2 - MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4 × 6.4 mm 2, and the tested chip can run at maximum 43.5 MHz clock rate.
AB - MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4 × 6.4 mm 2, and the tested chip can run at maximum 43.5 MHz clock rate.
UR - http://www.scopus.com/inward/record.url?scp=0032599267&partnerID=8YFLogxK
M3 - 會議論文
AN - SCOPUS:0032599267
SN - 1524-766X
SP - 46
EP - 49
JO - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
JF - International Symposium on VLSI Technology, Systems, and Applications, Proceedings
T2 - Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications
Y2 - 7 June 1999 through 10 June 1999
ER -