Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

C. L. Yang, C. H. Tsai, C. I. Li, C. Y. Tzeng, G. P. Lin, W. J. Chen, Y. L. Chin, C. I. Liao, M. Chan, J. Y. Wu, E. R. Hsieh, B. N. Guo, S. Lu, B. Colombeau, S. S. Chung, I. C. Chen

研究成果: 雜誌貢獻期刊論文同行評審

9 引文 斯高帕斯(Scopus)

摘要

In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation.

原文???core.languages.en_GB???
文章編號6289339
頁(從 - 到)1444-1446
頁數3
期刊IEEE Electron Device Letters
33
發行號10
DOIs
出版狀態已出版 - 2012

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