Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance

M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, P. D. Ye

研究成果: 書貢獻/報告類型會議論文篇章同行評審

33 引文 斯高帕斯(Scopus)

摘要

Steep-slope MoS2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor = 37.6 mV/dec and minimum SSRev = 42.2 mV/dec. A second minimum of SSRev as low as 8.3 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation.

原文???core.languages.en_GB???
主出版物標題2017 IEEE International Electron Devices Meeting, IEDM 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面23.5.1-23.5.4
ISBN(電子)9781538635599
DOIs
出版狀態已出版 - 23 1月 2018
事件63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States
持續時間: 2 12月 20176 12月 2017

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
ISSN(列印)0163-1918

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???event.eventtypes.event.conference???63rd IEEE International Electron Devices Meeting, IEDM 2017
國家/地區United States
城市San Francisco
期間2/12/176/12/17

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