The authors presents a test pattern generator, SLOPE, based on the stop line oriented path end algorithm, for combinational digital circuits. It combines the advantages of FAN and FAST by utilizing a controllability measure and observability measure to assist guessing in the test generation process. With some strategies adopted in the algorithm, it generates tests with fewer number of backtrackings. Benchmark circuits run with SLOPE show that it outperforms PODEM and FAN for most circuits.
|主出版物標題||Proceedings - IEEE International Symposium on Circuits and Systems|
|發行者||Publ by IEEE|
|出版狀態||已出版 - 1988|
|名字||Proceedings - IEEE International Symposium on Circuits and Systems|