Single-fault fault collapsing analysis in sequential logic circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen

研究成果: 書貢獻/報告類型會議論文篇章同行評審

1 引文 斯高帕斯(Scopus)


A study of fault collapsing for synchronous sequential circuits is presented. Two phenomena, self-hiding and delay-reconvergence, which invalidate the combinational fault dominance relationship in sequential circuits are identified. These phenomena are caused by the existence of feedback paths and storage elements in sequential circuits. From this analysis, a single-fault fault-collapsing procedure for synchronous irredundant sequential circuits is proposed to reduce the faults for which test has to be generated. This procedure can be applied not only to a nonscan mode circuit, but also to a full-scan and a partial-scan mode circuit by cutting the inputs and outputs of scannable D flip-flops as the primary outputs and inputs of the circuit, respectively. This procedure has been applied to collapse faults for the 31 benchmark sequential circuits, and a 57% reduction in the number of faults as compared with the total number of original faults has been obtained.

主出版物標題Digest of Papers - International Test Conference
發行者Publ by IEEE
出版狀態已出版 - 9月 1990
事件Proceedings - International Test Conference 1990 - Washington, DC, USA
持續時間: 10 9月 199014 9月 1990


名字Digest of Papers - International Test Conference


???event.eventtypes.event.conference???Proceedings - International Test Conference 1990
城市Washington, DC, USA


深入研究「Single-fault fault collapsing analysis in sequential logic circuits」主題。共同形成了獨特的指紋。