Single chip implementation of the 1.6 Kbps speech vocoder

Jia Ching Wang, Jhing Fa Wang, Han Chiang Chen

研究成果: 雜誌貢獻會議論文同行評審

3 引文 斯高帕斯(Scopus)


In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 Kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application.

頁(從 - 到)V-597-V-600
期刊Proceedings - IEEE International Symposium on Circuits and Systems
出版狀態已出版 - 2000
事件Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
持續時間: 28 5月 200031 5月 2000


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