Simultaneous floorplanning and buffer block planning

I. Hui-Ru Jiang, Yao Wen Chang, Jing Yang Jou, Kai Yuan Chao

研究成果: 書貢獻/報告類型會議論文篇章同行評審

11 引文 斯高帕斯(Scopus)

摘要

As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect delay and reduce the number of buffers needed.

原文???core.languages.en_GB???
主出版物標題Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面431-434
頁數4
ISBN(電子)0780376595
DOIs
出版狀態已出版 - 2003
事件Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
持續時間: 21 1月 200324 1月 2003

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2003-January

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???event.eventtypes.event.conference???Asia and South Pacific Design Automation Conference, ASP-DAC 2003
國家/地區Japan
城市Kitakyushu
期間21/01/0324/01/03

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