In this paper, we study the decoupled method which requires less memory on semiconductor device simulation. The decoupled method decouples the three equivalent circuits of semiconductor and solves them sequentially. The three equivalent circuits are formed by formulating the three partial differential equations that describe the electrical behaviour of semiconductor. Since the decoupled method solves one equation in each stage, the decoupled method uses one-ninth memory space of the coupled method. When decoupling the three equivalent circuits, the decoupled method yields a boundary condition limitation. In order to overcome the limitation, we propose a compromising partial decoupled method which has complete boundary condition and requires four-ninth memory space of the coupled method. The three methods are compared for computational efficiency and accuracy in the simulation of BJT. The simulation results are identical.
|頁（從 - 到）||421-432|
|期刊||International Journal of Numerical Modelling: Electronic Networks, Devices and Fields|
|出版狀態||已出版 - 9月 2004|