Sensitisable-path-oriented clustered voltage scaling technique for low power

J. Y. Jou, D. S. Chou

研究成果: 雜誌貢獻期刊論文同行評審

6 引文 斯高帕斯(Scopus)

摘要

Because the average power consumption of CMOS digital circuits is proportional to the square of the supplied voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on ISCAS85 benchmark circuits. These experiments show that many more gates can be voltage scaled down in comparison with the original CVS technique. An additional 22% power reduction ratio over that of the original CVS technique is achieved.

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頁(從 - 到)301-307
頁數7
期刊IEE Proceedings: Computers and Digital Techniques
145
發行號4
DOIs
出版狀態已出版 - 1998

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