Self-sampled vernier delay line for built-in clock jitter measurement

Keyphrases

• Clock Jitter 100%
• Jitter Measurement 100%
• Vernier Delay Line 100%
• Line Structure 66%
• Chip Area 66%
• CMOS Process 33%
• Measurement Range 33%
• Circuit Design 33%
• Jitter Free 33%
• Analog Signal 33%
• Mixed-signal Circuits 33%
• Free Samples 33%
• Chip Frequency 33%
• On-board Clock 33%
• Built-in Test Circuit 33%

Engineering

• Electric Delay Lines 100%
• Chip Area 66%
• Test Circuit 33%
• Measurement Range 33%
• Circuit Design 33%
• Signal Circuit 33%