@inproceedings{75eb43eda3c347a689f55ee00fddc0d5,
title = "Self-sampled vernier delay line for built-in clock jitter measurement",
abstract = "For high-speed analog and mixed signal circuits, on-chip clock jitter measurement has been a challenge in recent years. Circuit resolution, chip area, and frequency range are critical specification for built-in-test (BIT) circuit design. In order to fulfill these requirements, the self-sampled vernier delay line (VDL) structure is proposed. Comparing with traditional VDL structure, there is no more jitter free sample clock used in this design. When the proposed circuit is designed in 14ps circuit resolution, only 500um*750um chip area is used for 100MHz to 400MHz measurement range in TSMC 0.35um CMOS process.",
author = "Cheng, {Kuo Hsing} and Huang, {Chan Wei} and Jiang, {Shu Yu}",
year = "2006",
language = "???core.languages.en_GB???",
isbn = "0780393902",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "1591--1594",
booktitle = "ISCAS 2006",
note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",
}