TY - JOUR
T1 - Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction
AU - Tu, Shang Wei
AU - Jou, Jing Yang
AU - Chang, Yao Wen
PY - 2005
Y1 - 2005
N2 - Inductance effects of on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. The finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.
AB - Inductance effects of on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. The finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.
UR - http://www.scopus.com/inward/record.url?scp=33749850567&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465541
DO - 10.1109/ISCAS.2005.1465541
M3 - 會議論文
AN - SCOPUS:33749850567
SN - 0271-4310
SP - 4134
EP - 4137
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1465541
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -