Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction

Shang Wei Tu, Jing Yang Jou, Yao Wen Chang

研究成果: 雜誌貢獻會議論文同行評審

6 引文 斯高帕斯(Scopus)

摘要

Inductance effects of on-chip interconnects have become more and more significant in today's high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. The finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.

原文???core.languages.en_GB???
文章編號1465541
頁(從 - 到)4134-4137
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態已出版 - 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 5月 200526 5月 2005

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