Resource-aware functional ECO patch generation

An Che Cheng, Iris Hui Ru Jiang, Jing Yang Jou

研究成果: 書貢獻/報告類型會議論文篇章同行評審

11 引文 斯高帕斯(Scopus)

摘要

Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.

原文???core.languages.en_GB???
主出版物標題Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1036-1041
頁數6
ISBN(電子)9783981537062
出版狀態已出版 - 25 4月 2016
事件19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
持續時間: 14 3月 201618 3月 2016

出版系列

名字Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

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???event.eventtypes.event.conference???19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
國家/地區Germany
城市Dresden
期間14/03/1618/03/16

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